Exemplary embodiments of the present invention relate to a semiconductor device fabrication technology, and more particularly, to a semiconductor device and a method for fabricating the same, which may substantially reduce the occurrence of gate induced drain leakage (GIDL) current.
As the degree of integration of a semiconductor device increases, a channel length decreases. Also, as the channel length decreases, the operation characteristics of the semiconductor device are gradually degraded.
FIG. 1 is a cross-sectional view illustrating a conventional semiconductor device.
Describing a conventional method for fabricating a semiconductor device, a threshold voltage regulation layer 19 for regulating a threshold voltage may be formed in a substrate 11 by implanting ion impurities. A gate 16 may be formed to have a structure in which a gate dielectric layer 12, a first gate electrode 13, a second gate electrode 14 and a gate hard mask layer 15 are stacked. Subsequently, spacers 17 may be formed on both sides of the gate 16. Junction regions 18 may be formed in the substrate 11 on both sides of the gate 16. Since the junction regions 18 may be formed through implantation of ion impurities and an annealing process, the gate 16 and the junction regions 18 may be formed to partially overlap with each other.
According to the conventional semiconductor device, since the gate 16 and the junction regions 18 may be formed to partially overlap with each other, gate-induced drain leakage (GIDL) current may occur in areas where the gate 16 and the junction regions 18 overlap with each other (see the reference character ‘A’). In detail, in the conventional semiconductor device having the above-described construction, even if a transistor of the semiconductor device is in an “off” state, that is, in a state in which a bias is not applied to the gate 16, electric fields may be created in the areas where the gate 16 and the junction regions 18 overlap with each other, and thus GIDL current may occur. Due to this fact, “off” state properties of the transistor of the semiconductor device may be degraded.
Furthermore, as a size of the transistor of the semiconductor device decreases, the GIDL current may increase because the impurity doping concentration of the threshold voltage regulation layer 19 may be increased so as to maintain a threshold voltage, and thus the “off” state properties of the transistor of the semiconductor device may be degraded.